1. Field of the Invention
This invention relates generally to technology for forming small geometry spacers in semiconductor devices, and more particularly, to use of polymer spacers in such technology.
2. Discussion of the Related Art
As semiconductor device dimensions continue to decrease, problems arise in, for example, the formation of small geometry spaces, as illustrated with reference to FIGS. 1-9. As shown in FIG. 1, a layer of photoresist 20 is patterned to form photoresist bodies 22, 24 on a substrate 26 of, for example, silicon nitride, silicon dioxide, metal, polysilicon or the like, formed on a base layer 28, which substrate 26 is to have a space or opening formed therein. Current photoresist patterning technology limits the distance A between adjacent sidewalls 30, 32 of the photoresist bodies 22, 24 to a certain minimum (FIG. 1). When an anisotropic etch step is undertaken, using the photoresist bodies 22, 24 as a mask, the dimension A of the space 34 formed in the substrate 26 by such etching step is determined by the distance A between the sidewalls 30, 32 of the photoresist bodies 22, 24, limited, as pointed out about, by current photoresist patterning technology. Thus, the dimension A of the space 34 formed in the substrate 26 (FIG. 2) may well be greater than desired.
An attempt to overcome this problem is illustrated in FIGS. 3-6. As shown in FIG. 3, a substrate 40 in which a space or opening is to be formed is provided on a base layer 42. The substrate 40 has provided thereon an oxide layer 44, which in turn has a layer of photoresist 46, patterned into photoresist bodies 48, 50 thereon. An anisotropic etch step of the oxide layer 44 is undertaken, using the photoresist bodies 48, 50 as a mask (FIG. 4), to form oxide layer bodies 52, 54, typically of high aspect ratio. After removal of the photoresist 48, 50, an oxide layer 56 is provided over the resulting structure by chemical vapor deposition (FIG. 5), and an etching step is undertaken to form spacers 58, 60, 62, 64 on the respective sidewalls 66, 68, 70, 72 of the oxide bodies 52, 54 (FIG. 6). However, a number of problems exist in this process.
Initially, because of the high aspect ratio of the oxide bodies 52, 54, deposition of a properly conformal layer over the structure is problematical. Furthermore, typically, the portions 56A of the oxide layer 56 overlying the substrate 40 and the tops 57, 59 of the oxide bodies 52, 54 are substantially thicker than those portions 56B along the sidewalls 66, 68, 70, 72 of the oxide bodies 52, 54. When an anisotropic etch is undertaken to form spacers 58, 60, 62, 64 on the respective sidewalls 66, 68, 70, 72 of the oxide bodies 52, 54 (FIG. 6), the etching process must be continued for long enough to remove the entire thickness of the portions 56A from over the tops 57, 59 of the oxide bodies 52, 54 and from over the substrate 40. Even though an anisotropic etch is undertaken, a substantial amount of the oxide portions 56B on the sidewalls 66, 68, 70, 72 of the oxide bodies 52, 54 is also etched away, reducing the advantage which might have been obtained if the spacers 58, 60, 62, 64 were of full width.
A further problem is that upon an oxide layer 56 being provided on a low k body (oxide bodies 52, 54), the dielectric coefficient will drop. Additionally, there may exist interface problems between the spacers 58, 60, 62, 64 and oxide bodies 52, 54.
It will also be noted that a relatively large number of steps are required in practicing the above-described process.
FIGS. 7-9 illustrate an attempt to overcome the above described problems.
Again, a layer of photoresist 80 is patterned on a substrate 82 of, for example, silicon nitride, silicon dioxide, metal, polysilicon or the like (FIG. 7), to form photoresist bodies 84, 86. The substrate 82 is formed on a base layer 88, and the substrate 82 is again to have a space or opening formed therein. Prior to an etching step of the substrate 82, however, an oxide layer 90 is deposited on the structure by chemical vapor deposition (FIG. 8), with the idea that such oxide layer 90 will be anisotropically etched to form spacers 92, 94, 96, 98 on respective sidewalls 100,102,104,106 of the photoresist bodies 84, 86, which would in turn determine a dimension B between the adjacent spacers 94, 96 which is smaller (FIG. 9) than the dimension A between the adjacent sidewalls 30, 32 of the photoresist bodies 22, 24 as shown above in FIG. 1. However, it has been found that because of the high temperature involved in the deposition of the oxide layer 90 on the structure of FIG. 3, i.e., 200-400xc2x0 C. or more, the photoresist bodies 84, 86 will flow or otherwise be damaged, causing the entire process to fail, and also causing contamination of the oxide deposition chamber. Additionally, even if these problems could be overcome, it is problematical to simultaneously remove photoresist and oxide 92, 94, 96, 98 later in the process without damaging the underlying layer.
Therefore, what is needed is a process for overcoming the above problems in formation of small geometry spaces in semiconductor devices.
The present invention is a method of forming an opening in a substrate. Initially, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide at least first and second photoresist bodies having respective adjacent first and second sidewalls. A polymer layer is provided over the resulting structure in a low-temperature conformal CVD deposition process. The polymer layer is etched to form first and second spacers on the respective adjacent first and second sidewalls of the first and second photoresist bodies. The substrate is then etched using the first and second spacers as a mask.
The present apparatus includes a substrate, first and second photoresist bodies on the substrate and having respective first and second adjacent sidewalls, and first and second spacers comprising polymer material on the first and second respective adjacent sidewalls of the first and second photoresist bodies.